Intel Mobile Road Map

From Mac Guides

This is a guide to the Intel mobile road map as it stands in mid 2008.

Contents 1 Basics 2 Non-Intel chipsets 3 CPUs (in order of introduction) 3.1 Merom (65 nm) — July 2006 3.2 Penryn (45 nm) — January 2008 3.3 Nehalem (45 nm) — Q3 2009 3.4 Westmere (32 nm) — H1 2010 3.5 Sandy Bridge (32 nm) — H1 2011 3.6 Ivy Bridge (22 nm) — 2011 3.7 Haswell (22 nm) — 2012 4 Chipsets (in order of introduction) 4.1 Santa Rosa — May 2007 4.2 Montevina — July 2008 4.3 Calpella — Q3 2009 4.4 Sandy Bridge — 2010

Basics

There are two components to the motherboard, the CPU and the Motherboard Chipset. The CPUs will only work in certain chipsets but there is overlap between them. Also, the chipset is based on the microarchitecture. The current microarchitecture (for the last few years) has been "Core" (Core 2) microarchitecture. Nehalem (Core i7) is the next generation microarchitecture, and Sandy Bridge is the microarchitecture successor to Nehalem.

Note: Nehalem is an exception in the naming scheme in that it refers to both a processor (Clarksfield, Auburnsdale), a chipset (Calpella), and a microarchitecture (Nehalem). Most people refer to it's chipset properties though when mentioning it.

Second Note: To be extremely accurate, the chipsets that are noted are actually called platforms - ie. Santa Rosa platform, Montevina platform, Calpella platform, etc. A platform has three components - the CPU, the motherboard chipset, and the wireless network interface. But for layman's usage of these terms most people use the motherboard chipset name (Cantiga) as the platform name (Montevina), which while not technically correct is the way it is used on these forums so the same thing has been done here. The confusion arises when discussing future platforms (of which there may be one large one - notably Calpella, which is based on Nehalem processors), but which may have multiple motherboard chipsets (currently unknown names of future chipsets but there are likely others coming in the future).

Intel's roadmap alternates between die shrinks and new microarchitectures, one of which happens roughly every year. This is called "tick-tock," and each "tick" is a die shrink and each "tock" is a new microarchitecture.

Non-Intel chipsets

It has been rumored by AppleInsider that future Macs will not be using Montevina and future Intel chipsets, but other chipsets either designed by Apple or from AMD or VIA. It is noted that Apple is very likely to continue using Intel CPUs in the future though.

CPUs (in order of introduction)

Merom (65 nm) — July 2006

• Fits in Santa Rosa Chipset
• Designed for processing power

Penryn (45 nm) — January 2008

• Fits in Santa Rosa and Montevina chipsets
• Designed for power efficiency
• Features:

1. Support for SSE4 instruction set (beneficial for media applications that support this (video encoding work, etc))
2. 5-15% performance increase over Merom
3. Lower power consumption = More battery life
4. Higher L2 Cache on certain chips
5. By the end of 2008, dual-core: 25/35/45 W, quad-core: 35/45 W. 25 W dual-cores are also available in a SFF (small form factor) package that enables smaller laptops. This delivers a wide variety of CPUs for the Montevina chipset

Nehalem (45 nm) — Q3 2009

• Fits in Calpella Chipset
• Features (rumored):

1. Intel Quick Path Interconnect: Nehalem processors will utilize a new point-to-point processor interconnect called the Intel QuickPath Interconnect. This replaces the outdated FSBs which Intel has been using for many years and directly connect the RAM to the CPU
2. HyperThreading: Each core has two threads which means a quad-core Nehalem CPU would have eight virtual cores
3. Scalable Processing ability: The Nehalem CPU is apparently able to utilize as few or as many cores as needed for the tasks and programming infrastructure it has to process. This means that if a program is not optimized to use multiple cores (very common) then the cores that are being used could be overclocked and the other cores could be underclocked to remain within the heat specifications of the CPU. This would be the first truly scalable Intel processor.
4. On-Die Cache Controller
5. L1, L2, and L3 Cache
6. Possible on board graphics controller
7. Intel considers Nehalem the most dramatic change in Intel microarchitecture since the Pentium Pro in 1996

• The two processors (rumored) to be introduced in Q3 2009 are:

1. Auburnsdale: Dual-Core, 4 MB L3 Cache, 35-45 W TDP, onboard GPU core
2. Clarksfield: Quad-Core, 8 MB L3 Cache, 45-55 W TDP, no onboard GPU core
3. Note that due to the different chipsets, the Nehalem processors have equivalent heat output to a Penryn processor 10 W less.
4. It has been said that mobile Nehalem may be made on a 32 nm process, delivering higher performance for lower power consumption.

Westmere (32 nm) — H1 2010

• Formerly known as Nehalem-C
• Possibly fits in Calpella, Sandy Bridge Chipsets, but unknown currently
• Will feature AES-NI, a set of instructions that speeds up Advanced Encryption Systems

Sandy Bridge (32 nm) — H1 2011

• Currently unnamed, but Sandy Bridge (also the name of the unnamed chipset that will support it) is a common term used to refer to it
• Like "Nehalem" and "Westmere," "Sandy Bridge" refers to all Sandy Bridge processors.
• Due in 2010-2011
• Fits in Sandy Bridge chipset
• Focuses on power efficiency
• 4 to 8 cores at up to 4 GHz (up to 224 GFLOPS), although these may not be the mobile processors
  • DP server version has 6 cores and 12 threads
• 512 KB L2 cache/core, 2-3 MB L3 cache/core
• AVX (Advanced Vector Extensions) — Powerful version of SSE that enables 3- to 4-operand instructions on a 256-bit data path. So the peak DP FLOPS/clock is increased from 4 to 7.
• 0-512 MB integrated DRAM with 64 GB/s bandwidth
• Each QuickPath link has 17 GB/s bandwidth
• Dynamic Turbo — If the platform is fairly cool, then the processor can overclock while still maintaining acceptable levels of total platform TDP
• 22 nm shrink presumably due in 2011

Ivy Bridge (22 nm) — 2011

• Shrink of Sandy Bridge

Haswell (22 nm) — 2012

• New microarchitecture succeeding Sandy Bridge.

Chipsets (in order of introduction)

Santa Rosa — May 2007

• Based on "Core" microarchitecture
• Utilizes Crestline chipset
• 4th Generation Centrino Platform
• Houses Merom and Penryn CPUs
• Increased FSB from 667 MHz to 800 MHz

Montevina — July 2008

• Processors are based on "Core" microarchitecure
• Utilizes Cantiga chipset
• 5th Generation Centrino Platform
• Houses Penryn CPUs
• Features:

1. 40% smaller, to pave the way for slimmer and lighter notebooks
2. Supports dual-core Penryn processors up to 3.06 GHz and quad-core up to 2.53 GHz
3. Lower power requirements
4. 1066 MHz FSB (compared to 800 MHz for Santa Rosa)
5. DDR3 RAM clocked up to 1066 MHz (compared to DDR2 up to 667MHz on Santa Rosa)
6. Support for Intel Turbo Memory (optional on Santa Rosa)
7. Onboard gigabit ethernet
8. WiMax

Calpella — Q3 2009

• Due in Q3 '09 (with introduction of new chips)
• This is what most people are referring to when they say they are waiting for Nehalem!
• Utilizes an unnamed chipset
• 6th Generation Centrino Platform
• Houses Nehalem and possibly Westmere CPUs (but newer chipsets may need to be developed to hold Westmere CPUs)
• Features:

1. Calpella is designed for maximization of the raw processing power of Nehalem chips by eliminating the bottleneck of the FSB (front side bus) and replacing it with an IMC (integrated memory controller)
2. Note that the QuickPath interconnect featured on high-end desktop and server chips is not featured in Calpella, instead, there will be a DMI bus interface
3. Supports DDR3 RAM up to 1333 MHz - important because a major bottleneck in current systems is the FSB which connects the RAM and CPU. The Nehalem+Calpella boards seek to eliminate that bottleneck based off of the new design and the RAM speeds will likely be quite noticeable and contribute to increased performance. Currently (early-2008) RAM and FSB upgrades are only slightly noticeable in the range of 20-30% improvement in speeds.
4. Native support for Blu-Ray (and video encoding/decoding tasks)
5. Native support for SSDs, hybrid drives
6. WiMax
7. Nehalem chips feature 2-8 cores, but Calpella supported Nehalem chips will support 2-4 cores as of right now.

Sandy Bridge — 2010

• No chipset names are known as of now, this is the name of the underlying CPU microarchitecture, but commonly people use this name to describe the chip as well
• The successor to the Nehalem microarchitecture chipsets
• Chipset northbridge is not called a MCH, but the "Sandy Bridge System Agent"
• Sandy Bridge Chipset to support 32nm chips: Due in 2010
• Sandy Bridge Chipset to support 22nm chips: Due in 2011